Methods of Packaging a Semiconductor Die and Package Formed by the Methods

ABSTRACT

A method of packaging a semiconductor die ( 20 ). The method comprises mounting a semiconductor die ( 20 ) to a die attach pad ( 34 ) on a carrier ( 10 ) and electrically coupling an electrode ( 36 ) of the semiconductor die ( 20 ) and a contact pad ( 16 ) on the carrier ( 10 ) with a clip ( 54 ) carried by a sacrificial substrate ( 58 ). The method further comprises removing the sacrificial substrate ( 58 ) to release the clip ( 54 ). The method may be extended to accommodate a carrier ( 10 ) having multiple device regions ( 12, 13 ) each with a die attach pad ( 34 ) and a contact pad ( 16 ) for mounting multiple semiconductor die ( 20 ).

The present invention relates generally to chip packaging and, inparticular, methods of forming die packages that utilize clipbonding toelectrically couple an electrode of a semiconductor die with a contactpad of a device region on a carrier.

Semiconductor die or chips carrying an integrated circuit may bepackaged into a chip package and then surface mounted to a substrate,such as a printed wiring board (PWB) or printed circuit board (PCB), toform an electronic assembly. The packaging of a semiconductor dieprovides several important functions. Among those functions areprotection of the semiconductor die against moisture and other damagingenvironmental elements, electrical connection to external circuitry, andthermal management of the heat load generated by the semiconductor die.

A common type of chip package is a surface mount device (SMD) thatincludes contact pads that are connected by solder bonding tocomplementary contact pads on the printed wiring board. The chip packageis manipulated by a placement machine onto a specified location on theprinted wiring board and subsequently coupled electrically by solderbonds to the printed wiring board. The printed wiring board providesboth the physical structure for mounting and holding the chip package aswell as a pattern of conductive traces extending from the contact padsto electrically interconnect the semiconductor chip inside the chippackage with other components mounted to the printed wiring board, suchas discrete passive components or other semiconductor chips. Theseadditional components include circuitry used for supplying power to,controlling, or otherwise interacting electronically with the integratedcircuit of the semiconductor chip inside the chip package.

To form a chip package, the semiconductor chip is mounted to a frontside of a metal carrier, such as a leadframe. Conductive paths areestablished between contact or bond pads on the semiconductor chip andcontact or bond pads also on the front side of the carrier. One approachfor establishing these conductive paths is a wire bonding process inwhich individual leads extend from the chip bond pads outwardly beyondthe peripheral edges of the chip to the carrier bond pads. The leads,which are defined by fine wire, are bonded at each opposite end to thecorresponding bond pads. The conductive paths established by the leadsand bond pads supply chip-to-carrier interconnections for power andsignal distribution. The coupled semiconductor die and carrier areencapsulated in a protective body of molding material to form a sealedpackage that protects the semiconductor die and leads. The carriercontact pads are exposed by the encapsulated package for mounting thepackage to a printed wiring board.

Power electronics packages provide mechanical support, deviceprotection, cooling, and electrical connection and isolation for powersemiconductor die that have high current capability. The overallperformance of a power electronics package is affected by the packaging.In particular, power semiconductor die include bond pads on a topsurface that are typically constituted by an aluminum alloy containing aminor percentage of silicon. The aluminum bond pads typically provide atopside connection with the source and gate of the power semiconductordie. A conventional wire bond process may be used to form an electricalconnection with the aluminum bond pads. However, a wire-bond connectionhas a limited contact area and, therefore, is a source of significantelectrical resistance and heat generation during device operation.

Due to the various disadvantages of wire bonding, package manufacturershave resorted to the use of conductive clips as a substitute for wirebonds to establish electrical contacts with the aluminum bond pads ofthe power semiconductor die inside the die package. The conductive clipis typically placed individually into a position overlying the powersemiconductor die and bonded with the aluminum contact pad with aquantity of adhesive or solder. The bond extends over a much largercontact area than available with wire bonding, which improves thecurrent carrying capability of the contact. However, conventionalclipbonding operations require a discrete pick and place operation foreach of multiple power semiconductor die each having a rear surfaceattached to a die attach pad on a leadframe. This significantly limitsprocess throughput and hampers high volume packaging operations.Alternatively, another top leadframe may be bonded with the aluminumcontact pads of each of multiple power semiconductor die attached to alower leadframe and then bent by punching during assembly to define theconductive clip. Similarly, this significantly limits process throughputand hampers high volume packaging operations, which increases the costof packaging. For high yield during assembly, the top leadframe must beaccurately aligned with the aluminum contact pad of each of the pluralsemiconductor die. After assembly and encapsulation with moldingcompound, the top leadframe represents an additional metal object thatmust be cut during singulation into discrete packages.

What is needed, therefore, is a method for clipbonding with asemiconductor die inside a die package that overcomes the disadvantagesof conventional packaging methods that rely on conductive clips toestablish electrical contacts with the bond pads of a semiconductor dieinside the die package.

In one embodiment of the present invention, a method of packaging asemiconductor die comprises mounting a semiconductor die to a die attachpad on a carrier and electrically coupling a first portion of a clipcarried by a sacrificial substrate with an electrode of thesemiconductor die. The method further comprises removing the sacrificialsubstrate to release the clip.

In another embodiment of the present invention, a method of packaging aplurality of semiconductor die comprises mounting each of thesemiconductor die to a die attach pad of a corresponding one of aplurality of device regions on a carrier. The method further compriseselectrically coupling a first portion of each of a plurality of clipscarried by a sacrificial substrate with an electrode of a correspondingone of the semiconductor die and then removing the sacrificial substrateto release the clips.

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments of the invention and,together with a general description of the invention given above and thedetailed description of the embodiments given below, serve to explainthe principles of the invention.

FIGS. 1 through 5 are diagrammatic views of a pair of device regions ofa carrier with plural device regions depicted at various processingstages in accordance with an embodiment of the present invention.

FIG. 3A is a diagrammatic side view of the carrier of FIG. 3.

The present invention provides methods for forming a package for a powersemiconductor die. The present invention will now be described ingreater detail by referring to the drawings that accompany the presentapplication.

With reference to FIG. 1 and in accordance with an embodiment of thepresent invention, a leadframe or carrier 10 includes a matrix or arrayof device regions, of which a pair of device regions 12, 13 is shown inFIG. 1, arranged across a generally planar surface 14. As used herein,“vertical” means a direction substantially perpendicular to surface 14and “horizontal” means a direction substantially parallel to surface 14.A plurality of contact pads 16, 18 are located adjacent to each of thedevice regions 12 and, if present, other device regions of the carrier10. The contact pads 16, 18 are employed to establish a connection witha semiconductor chip or die 20 attached to each of the device regions12, 13. The following description of device region 12 applies equally todevice region 13, which is substantially identical to device region 12.Additional portions (not shown) of the carrier 10 couple the deviceregions 12, 13 and the contact pads 16, 18 to form a continuousstructure. For example, carrier 10 may constitute a carrier described incommonly-assigned U.S. patent application Ser. Nos. 10/510,591 and10/510,558, each of which is hereby incorporated by reference herein inits entirety.

Contact pad 16 of device region 12 includes a first metallization layer22 on the same side of the carrier 10 as the semiconductor die 20 and asecond metallization layer 24 on an opposite side of the carrier 10 usedto establish an electrical contact between the finished package (notshown) and a substrate, such as a printed wiring board. Similarly,contact pad 18 of device region 12 includes a first metallization layer26 on the same side of the carrier 10 as the semiconductor die 20 and asecond metallization layer 28 on an opposite side of the carrier 10. Thesecond metallization layers 24, 28 are used to establish an electricalcontact between the semiconductor die 20 inside the finished package(not shown) and a substrate (not shown), such as a printed wiring board.

An amount or quantity 30 of a conductive bonding substance, such as aconductive adhesive or a solderable material such as solder paste orsolder, is applied to an exposed surface 21 of the first metallizationlayer 22 of the contact pad 16. Another amount or quantity 32 of theconductive bonding substance is applied to an exposed surface 25 of thesecond metallization layer 26 of the contact pad 18. Among otherfactors, the exact volume or mass of each of the quantities 30, 32 iscontingent upon the area across which electrical, mechanical, andthermal contact is established.

The semiconductor die 20 is attached to a die attach pad 34 on thecarrier 10 that is located adjacent to the contact pads 16, 18. Thesemiconductor die 20 includes a first major electrode 36 disposed on atop surface 35 distal to the die attach pad 34 and a second majorelectrode 38 (FIG. 3A) disposed on a bottom surface 39 (FIG. 3A)proximate to the die attach pad 34. Semiconductor die 20 also includes asmaller control electrode 40 disposed on the top surface 35 andelectrically insulated from the first major electrode 36. If thesemiconductor die 20 is a power transistor, the first major electrode 36is a source contact pad, the second major electrode 38 constitutes adrain contact pad, and the control electrode 40 is a gate contact pad.In use, the control electrode 40 modulates the current flowing betweenthe first and second electrodes 36, 38 in response to control signalsfrom an external controller as understood by a person having ordinaryskill in the art. The first major electrode 36 and the control electrode40 may be composed of an aluminum alloy containing a minor amount ofsilicon.

The second electrode 38 is coupled with the die attach pad 34 by aconductive layer 42 (FIG. 3A) of a conductive adhesive or ahigh-temperature, heat-conductive solder, often a eutectic solder.Conductive layer 42 provides a direct electrical connection between thesecond electrode 38 and the die attach pad 34.

Disposed on an exposed surface 43 of the first electrode 36 is an amountor quantity 44 of a conductive bonding substance, such as a conductiveadhesive or a solderable material such as solder paste or solder.Another amount or quantity 46 of the conductive bonding substance isdisposed on the exposed surface of the control electrode 40. Among otherfactors, the volume or mass of each of the quantities 44, 46 iscontingent upon the area across which electrical, mechanical, andthermal contact is established.

With reference to FIG. 2 in which like reference numerals refer to likefeatures in FIG. 1 and at a subsequent processing stage, a patterned andpre-formed top frame 50 is located in a generally overlying relationshipspaced from the carrier 10. The top frame 50 is moved vertically asindicated by arrows 52 into a contacting relationship with thesemiconductor die 20 and the contact pads 16, 18.

The top frame 50 includes clips 54, 56 carried on and bonded with asacrificial substrate 58. The sacrificial substrate 58 is composed of amaterial that may be etched by an appropriate wet or dry etching processselective to the conductive material (e.g., metal) constituting theclips 54, 56 and without damaging the carrier 10. Similarly, theconductive material or materials constituting clips 54, 56 may be etchedby an appropriate wet or dry etching process selective to the materialconstituting the sacrificial substrate 58 and without damaging thecarrier 10. The clips 54, 56 are separated from each other by regions ofthe substrate 58. When substrate 58 is removed, as described below, theclips 54, 56 are electrically isolated from each other.

The clips 54, 56 are formed from a layer of conductive material having anominally uniform thickness that is deposited by a conventional process,such as electroplating, or laminated by a conventional process on thesacrificial substrate 58. This layer is patterned to define the clips54, 56 by a conventional lithography and wet or dry etching process thatprotects portions of the metal layer with an etch mask and removesunprotected portions of the layer selective to the material constitutingthe sacrificial substrate 58. Etching is a subtractive process in thecourse of which unmasked portions of the layer are either dissolved inliquid chemicals (i.e., wet etching) or converted into volatile gaseouscompound (i.e., dry etching).

In one embodiment of the present invention, the metal sheet patternedinto clips 54, 56 is composed of copper or a copper alloy of which thebulk of the alloy composition is copper and the sacrificial substrate 58is composed of aluminum or an aluminum alloy of which the bulk of thealloy composition is aluminum. In this instance, the pattern can beapplied lithographically on the copper or copper alloy followed by a wetcopper etch selective to aluminum.

Clip 54, which is larger in area than clip 56, includes a major pad 60and an appendage or arm 62 extending away from the major pad 60. Clip 56consists of a strip 64 that extends on sacrificial substrate 58generally in the same direction as arm 62 of clip 54. The top frame 50includes a pair of smoothly-curved and generally parallel bends 66, 68that are formed by deforming the top frame 50. Bend 66 operates tochange the elevation of a free end 70 of the arm 62 and an end 72 ofstrip 64 to account for relative differences in elevation among the topsurface 35 of the semiconductor die 20 and the exposed top surfaces 21,25 of the contact pads 16, 18, respectively.

With reference to FIG. 3 in which like reference numerals refer to likefeatures in FIG. 2 and at a subsequent processing stage, the top frame50 is moved such that quantities 44, 46 of the conductive bondingsubstance contact a bottom side of the major pad 60 of clip 54 and abottom side of an end 74 of the strip 64, respectively. Because of thepresence of the bend 66 in the top frame 50, the free end 70 of the arm62 of clip 54 and the end 72 of strip 64 of clip 56 contact thequantities 30, 32 of the conductive bonding substance. If the conductivebonding substance is solder or solder paste, a soldering process,generally accomplished by wave soldering, infrared (1R) reflowsoldering, convective IR reflow soldering, or vapor phase reflowsoldering, is used to establish metallic or inter-metallic bonds betweenthe clips 54, 56, the contact pads 16, 18, and the semiconductor die 20.If the conductive bonding substance is an adhesive, a curing process,such as heating, is used to establish corresponding adhesive bonds.

With reference to FIG. 4 in which like reference numerals refer to likefeatures in FIG. 3 and at a subsequent processing stage, the sacrificialsubstrate 58 is removed using a wet or dry etching process that removesthe material constituting sacrificial substrate 58 selective to thematerial constituting the carrier 10 and the clips 54, 56. The clips 54,56 are thereby released from the substrate 58 and, after release, areelectrically isolated from each other. For example, if the clips 54, 56are composed of copper or a copper alloy and the sacrificial substrate58 is aluminum or an aluminum alloy, an appropriate wet etchant is aheated alkali bath of potassium hydroxide (KOH) or sodium hydroxide(NaOH) solution for a time sufficient to completely etch away thesubstrate 58, which leaves the clips 54, 56 as independent, electricallyisolated structures and frees the clips 54, 56 from substrate 58. Theetching time will depend upon the thickness of the substrate 58. Heatingthe etchant bath to, for example, 50° C. elevates the etching rate and,hence, decreases the etching time.

With reference to FIG. 5 in which like reference numerals refer to likefeatures in FIG. 4 and at a subsequent processing stage, the contacts16, 18 are readied by standard fabrication processes for electricallycoupling the semiconductor die 20 with a substrate, such as a printedwiring board (not shown). Die packages 80, 82 are completed by applyinga body 84 of molding compound to the carrier 10 by any suitable moldingtechnique as understood by a person having ordinary skill in the art.For example, the body 84 may be applied to the carrier 10 by overmoldingin a suitable mold tray. The body 84 of molding compound is cured and atleast partially hardened, using techniques that are also known in theart, such as oven curing. For example, the molding compound body 84 maybe formed by transfer or injection molding over the carrier 10. Themolding compound body 84 fully encapsulates the carrier 10, contact pads16, 18, and semiconductor die 20 and fills any open spaces with theexception of the second metallization layers 24, 28 of contact pads 16,18, respectively, which are exposed and not otherwise contaminated byextraneous molding compound.

The die packages 80, 82, each of which includes one semiconductor die20, are separated or singulated along a line between the device regions12, 13 by cutting through the body 84 of molding compound. Thesingulating operation may be performed using a technique, such as sawingusing a wafer saw, known to a person having ordinary skill in the art.The die packages 80, 82 may be electrically mounted, after beingsingulated, to the substrate (e.g., printed wiring board). The outermolding compound body 84 prevents the ingress of environmentalcontaminants.

While the present invention has been illustrated by a description ofvarious embodiments and while these embodiments have been described inconsiderable detail, it is not the intention of the applicants torestrict or in any way limit the scope of the appended claims to suchdetail. Additional advantages and modifications will readily appear tothose skilled in the art. Thus, the invention in its broader aspects istherefore not limited to the specific details, representative apparatusand method, and illustrative example shown and described. Accordingly,departures may be made from such details without departing from thespirit or scope of applicants' general inventive concept.

1. A method of packaging a semiconductor die, comprising: mounting asemiconductor die to a die attach pad on a carrier; electricallycoupling a first portion of a first clip carried by a sacrificialsubstrate with a first electrode of the semiconductor die; and removingthe sacrificial substrate to release the first clip (54).
 2. The methodof claim 1 further comprising: electrically coupling a second portion ofthe first clip with a first contact pad on the carrier before thesacrificial substrate is removed.
 3. The method of claim 2 wherein thefirst electrode and the first contact pad are located in differenthorizontal planes on the carrier, and further comprising: bending thesacrificial substrate so that the first and second portions of the firstclip have different elevations to compensate for the differenthorizontal planes of the first electrode the first contact pad.
 4. Themethod of claim 1 wherein electrically coupling the first portion of thefirst clip further comprises: applying a quantity of a conductiveadhesive to an first electrode on the semiconductor die; contacting thefirst portion of the first clip with the quantity of the conductiveadhesive; and curing the quantity of the conductive adhesive toadhesively couple the first portion of the clip with the firstelectrode.
 5. The method of claim 1 wherein electrically coupling thefirst portion of the first clip further comprises: applying a quantityof a solderable material to an first electrode on the semiconductor die;contacting the first portion of the clip with the quantity of thesolderable material; and reflowing the quantity of the solderablematerial to bond the first portion of the clip with the first electrode.6. The method of claim 1 wherein the sacrificial substrate is formedfrom a first material and the first clip is formed from a secondmaterial, and removing the sacrificial substrate further comprises:etching the sacrificial substrate to remove the first material selectiveto the second material.
 7. The method of claim 6 wherein the firstmaterial is aluminum or an aluminum alloy and the second material iscopper or a copper alloy, and etching the sacrificial substrate furthercomprises: immersing at least the sacrificial substrate in an alkalibath having a chemistry that reacts with the first material selectivelyto the second material.
 8. The method of claim 7 wherein the alkali bathcomprises a heated alkali bath of an aqueous potassium hydroxidesolution or an aqueous sodium hydroxide solution.
 9. The method of claim1 further comprising: depositing a layer of a conductive material on thesacrificial substrate; and patterning the layer to define the firstclip.
 10. The method of claim 9 wherein patterning the first layerfurther comprises: applying an etch mask to protect regions of the layercorrelated with a shape of the clip; and completely removing unprotectedregions of the layer with an etching process to transfer the shape fromthe etch mask to the layer.
 11. The method of claim 1 furthercomprising: overmolding the carrier with a body of molding compound toencapsulate the semiconductor die and the first clip and, thereby,define a die package.
 12. The method of claim 1 further comprising:electrically coupling a first portion of a second clip carried by thesacrificial substrate with a second electrode of the semiconductor die;electrically coupling a second portion of the second clip with a secondcontact pad on the carrier before the sacrificial substrate is removed;and removing the sacrificial substrate to release the second clip.
 13. Amethod of packaging a plurality of semiconductor die, comprising:mounting each of the semiconductor die to a die attach pad of acorresponding one of a plurality of device regions on a carrier;electrically coupling a first portion of each of a plurality of clipscarried by a sacrificial substrate with an electrode of a correspondingone of the semiconductor die; and removing the sacrificial substrate torelease the clips.
 14. The method of claim 13 further comprising:electrically coupling a second portion of each of the clips with acorresponding one of a plurality of contact pads on the carrier beforethe sacrificial substrate is removed.
 15. The method of claim 14 whereinthe electrodes and the contact pads are located in different horizontalplanes on the carrier, and further comprising: bending the sacrificialsubstrate so that the first and second portions of each of the clipshave different elevations to compensate for the different horizontalplanes of the electrodes and the contact pads.
 16. The method of claim13 wherein the sacrificial substrate is formed from a first material andthe clips are formed from a second material, and removing thesacrificial substrate further comprises: etching the sacrificialsubstrate to remove the first material selective to the second material.17. The method of claim 16 wherein the first material is aluminum or analuminum alloy and the second material is copper or a copper alloy, andetching the sacrificial substrate further comprises: immersing at leastthe sacrificial substrate in an alkali bath having a chemistry thatreacts with the first material selectively to the second material. 18.The method of claim 17 wherein the alkali bath comprises a heated alkalibath of an aqueous potassium hydroxide solution or an aqueous sodiumhydroxide solution.
 19. The method of claim 13 further comprising:depositing a layer of a conductive material on the sacrificialsubstrate; and patterning the layer to define the clips.
 20. The methodof claim 19 wherein patterning the first layer further comprises:applying an etch mask to protect regions of the layer correlated with ashape of each of the clips; and completely removing unprotected regionsof the layer with an etching process to transfer the shape of each ofthe clips from the etch mask to the layer.
 21. The method of claim 13further comprising: overmolding the carrier with a body of moldingcompound to encapsulate the plurality of semiconductor die and theclips.
 22. The method of claim 21 further comprising: separating thedevice regions from the carrier to define a plurality of die packageseach including a corresponding one of the device regions and acorresponding one of the semiconductor die.
 23. A semiconductor packagecomprising: a semiconductor die having an first electrode; a carriersupporting the semiconductor die, the carries including at least onedevice region having a die attach pad coupled with the semiconductor dieand a first contact pad, the first electrode of the semiconductor diebeing exposed when the semiconductor die is coupled with the die attachpad; a first clip electrically coupling the first contact pad with thefirst electrode of the semiconductor die, the first clip being supportedby a sacrificial substrate that is removed after the first clip isattached to the first contact pad and to the first electrode; and a bodyof molding compound at least partially encapsulating the device region,the semiconductor and the first clip.
 24. The semiconductor package ofclaim 23 wherein the semiconductor die further includes a secondelectrode and the device region of the carrier includes a second contactpad, and further comprising: a second clip electrically coupling thesecond contact pad with the second electrode of the semiconductor die,the second clip being supported by the sacrificial substrate that isremoved after the second clip is attached to the second contact pad andto the second electrode.
 25. The semiconductor package of claim 24wherein the body of molding compound at least partially encapsulates thesecond clip.